Business Overview

5. INFORMATION ON OUR GROUP 5. INFORMATION ON OUR GROUP
5.1 HISTORY AND BACKGROUND
5.1.1
Our Group’s Historical Overview We were incorporated in Malaysia under the Act on 22 August 2005 as a private limited company known as Pearl Discovery Sdn Bhd. On 3 October 2005, we changed our name to Key ASIC Sdn Bhd. Subsequently, we were converted into a public limited company on 13 June 2007 and assumed our present name. On 14 April 2006, we were awarded the MSC status by MDeC and are currently enjoying full income tax exemption under the pioneer status for a period of 5 years and renewable for another 5 years. Our Company is principally engaged in fabless high-end turnkey ASIC/SoC design services and development of IPs whilst our subsidiary is principally engaged in the business of providing manufacturing management services to fabless design companies, provide design-for-manufacturing and design-for­test consultation and the sale of wafer and SoC products. The manufacturing process of the chips is outsourced to foundries and manufacturing partners. We are able to provide design-to-manufacture services through close partnership with foundries and other test and packaging houses. We commenced operations on 22 August 2005 as a wholly-owned subsidiary of KAL. We started our design activity by designing IPs and also application specific SoC platforms. These IPs are essential building blocks for SoC chips for consumer electronic and communication applications. The consumer electronics applications include MP3, PMP, OVB, OVO, digital home gateway and image processing chips. The IPs for the communication applications includes VolP, xDSL, Wi-Fi and WiMAX. In the beginning of 2006, we developed and ported our first set of analogue IPs on 0.181J process technology of Silterra. Subsequently, the second set of IPs that we ported on 0.181J and 0.131J process technology of Silterra were ARM 926, ARM 946 CPU cores and interface IPs. Currently, we have more than 50 peripheral IP blocks developed and ported on Silterra’s 0.181J, 0.161J and 0.131J technology and some of the IPs were also developed and ported on other foundries such as TSMC. Our core competence is the capability of our design team to design SoC and ASIC from system specification and architectural level to GDS II. The key differentiator of our Company is our expertise in designing high performance, low power consumption and smaller size chips. We are also capable of designing low power chips for mobile devices. Currently, we have two operations in Malaysia and they are located in Petaling Jaya and Cyberjaya. As part of our 3-year business plan, we are focusing on developing our IPs to target consumer electronics and communication due to the growth of this market segment from the use of devices such as MP3, mobile phones, POA and portable players. With continuous push for performance, low power consumption and smaller die size for most hand held devices, we plan to port our IP and platforms to smaller IC size to 0.091J and 0.0651J in 2008 and 2009 respectively. We plan to expand our application platforms and plan to develop some IPs for new application needs. 5. INFORMATION ON OUR GROUP (CONT’Dj Our Group structure can be depicted as follows: Key ASIC  100%  KASSB
Further details on our Group’s business and industry are set out in Section 5.4 of this Prospectus. 5.1.2 Share Capital The present authorised share capital of our Company is RM100,000,000 comprising 1,000,000,000 Key ASIC Shares. The issued and paid-up share capital of our Company is RM60,300,000 comprising 603,000,000 Key ASIC Shares. As at the date of this Prospectus, neither our Company nor our subsidiary has any outstanding warrants, options, convertible securities and uncalled capital. Details of the changes in the issued and paid-up share capital of our Company since its incorporation are as follows: Total issued and paid up Date of No. of Type of Par share allotment shares shares value Consideration capital RM RM 22.08.2005 2 Ordinary 1.00 Subscriber shares 2 shares 05.04.2006 32,299,998 Ordinary 1.00 Capitalisation of 32,300,000 shares amount owing to holding company
14.07.2006 19,000,000 Preference 1.00 Issuance of ICPS 51,300,000 shares 04.10.2007 19,000,000 Ordinary 1.00 Conversion of ICPS 51,300,000 shares
19.11.2007 9,000,000 Ordinary 1.00 Rights Issue 60,300,000 shares 21.11.2007 603,300,000 Ordinary 0.10 Share Split 60,300,000 shares Our issued and paid-up share capital would subsequently increase to RM80,500,000 comprising 805,000,000 Shares following our Public Issue. 5. INFORMATION ON OUR GROUP (CONT’D) 5.2 LISTING SCHEME 5.2.1 Restructuring In conjunction with, and as an integral part of our Listing on the MESDAQ Market of Bursa Securities, we undertook a restructuring exercise involving the following: (i) Conversion of ICPS Our ICPS holders, namely AQSB and C1VSB have converted their ICPS amounting to 19,000,000 into ordinary shares based on the conversion of 1 new ordinary share of RM1.00 each in Key ASIC for every 1 existing ICPS held in Key ASIC. The conversion was completed on 4 October 2007, and resulted in our share capital being enlarged to RM51,300,000 comprising 51,300,000 ordinary shares of RM1.00 each in Key ASIC. The new ordinary shares of RM1.00 each in Key ASIC, with effect from the conversion date, rank equally in all respects with our eXisting issued and paid-up ordinary shares. This includes voting rights and entitlements to all rights, dividends and other distributions that we may subsequently declare after the conversion. (ii) Rights Issue We have implemented a renounceable rights issue of 9,000,000 new ordinary shares of RM1.00 each in Key ASIC at an issue price of RM1.00 per share on the basis of about 175 new ordinary shares of RM1.00 each in Key ASIC for every 1,000 eXisting ordinary shares of RM1.00 held in Key ASIC. The Rights Issue was completed on 19 November 2007 and resulted in our share capital being enlarged to RM60,300,000 comprising 60,300,000 ordinary share of RM1.00 in Key ASIC. (iii) Share Split Upon completion of the Rights Issue, we implemented a share split on the basis of 1 existing ordinary share of RM1.00 in Key ASIC held into 10 Key ASIC Shares. The Share Split was completed on 21 November 2007 and resulted in our number of shares increasing to 603,000,000 Key ASIC Shares. 5. INFORMATION ON OUR GROUP (CONT’D)
5.2.2 Public Issue In conjunction with the flotation of our Company on the MESDAQ Market of Bursa Securities, our Company will make available 202,000,000 Issue Shares as follows: (a) 10,000,000 of the Issue Shares available for application by the Malaysian public;
(b) 16,500,000 of the Issue Shares available for application by our eligible Directors, employees and business associates; and
(c) 175,500,000 of the Issue Shares available for private placement to institutional investors and selected investors.

5.2.3 Listing Thereafter, we will seek an admission to the Official List of the MESDAQ Market of Bursa Securities for the listing of and quotation for our entire enlarged issued and paid-up share capital of RM80,500,000 comprising 805,000,000 Key ASIC Shares. 5.3 SUBSIDIARY As at the date of this Prospectus, we have a subsidiary, namely KASSB, the details of which are as follows: Date and Issued and place of paid-up Effective Name incorporation capital interest Principal activities RM % KASSB 07.06.2007; 2 100.00 Provision of manufacturing Malaysia management services to fabless design companies, design-for­manufacturing and design-far-test consultation, and sale of wafer and SoC products As at the date of this Prospectus, we do not have any associated company. 5.3.1 KASSB (i) History and Business KASSB was incorporated in Malaysia under the Act on 7 June 2007 as a private limited company under its present name. KASSB is principally involved in the provision of manufacturing management services to fabless design companies, design-for-manufacturing and design-for-test consultation and sale of wafer and SoC products. KASSB commenced business operations since its incorporation. 5. INFORMATION ON OUR GROUP (CONT’D)
(ii) Share Capital The present authorised share capital of KASSa is RM100,OOO comprising 100,000 ordinary share of RM1.00 each in KASsa. The issued and paid-up share capital is RM2 comprising 2 ordinary share of RM1.00 each in KASsa. Changes in the issued and paid-up share capital of KASSa since its incorporation are as follows: No. of Total issued Date of ordinary Par and paid-up allotment shares value Consideration share capital RM RM 07.06.2007 2 1.00 Subscriber shares (iii) Substantial Shareholder KAssa is our wholly-owned subsidiary. (iv) Subsidiary and Associated Company As at the date of this Prospectus, KASSa does not have any subsidiary or associated company. 5.4 BUSINESS OVERVIEW Our Company is principally engaged in fabless high-end turnkey ASIC/SoC design services and development of IPs whilst our subsidiary is principally engaged in the business of providing manufacturing management services to fabless design company, providing design-far-manufacturing and design-far-test consultation, and the sale of wafer and SoC products. 5.4.1 Principal Products and Services Our Group’s design services include providing customers with one-stop design-to-manufacture integration services via our in-house capabilities and we have formed strategic partnerships with semiconductor foundries and other test and packaging houses. Through KASSa, we manage the entire design value chain starting from customers providing us with top-level technical specification and us providing architectural design down to outsourcing the fabrication process to a foundry. In this case, we act as a contractor to the customers. We add value to the intermediate stages of the development by organising foundry, integration and assembly, final test and shipment services in order to deliver volume production of final products, tested and packaged. Apart from the ASIC design, we also provide design-to­manufacturing and logistic services to the customers. Our complete SoC design flow covers system, front-end and back-end design, depending on the customers’ desired involvement in the SoC design. This can be seen as a one-stop turnkey solution to the customers. 5. INFORMATION ON OUR GROUP (CONT’D)
Customers’ engagement can begin at three different levels, ranging from high-level specification to GOS ” as follows: (a) Design from specification
Customers provide us with detailed specification of the ASIC and our design engineers will design from specifications at RTL codes, go through RTL simulations, perform synthesis and gate level simulations. Upon successful completion of the gate level simulation, we will perform the physical implementation, place and route, ORC/ERC extractions, and post layout timing analysis before producing a GOS ” file. From here, we can also deliver customers with tested and packaged chips or wafers through our collaboration with foundry and testing houses if customers desire.
(b) From Netlist
Additionally, customers can provide us with a thoroughly verified netlist and we will provide the place and route services and extraction. From here, we can also deliver customers with tested and packaged chips or wafers through our collaboration with foundry and testing houses if customers desire.
(c) From GDS II

Alternatively, customers can complete the entire design in-house and provide us with a GOS II file. From here, we can also deliver customers with tested and packaged chips or wafers through our collaboration with foundry and testing houses if customers desire. Through our KeylP services, we also offer customers access to IP from our pool of silicon-proven mixed-signal and digital IPs, including interface, IP blocks, CPU and DSP that is targeted for designs of PMP, MP3 players, cell phones, Wi-Fi, WiMAX, set top boxes, digital home media servers, multimedia, networking, VolP and telephone products. We design, develop and license our IPs to customers worldwide. We have developed a complete set of IPs, namely KeyWare targeted at the consumer electronics and communication segment. We also provide IP porting service and full custom IP design service to the exact specification from customers. Currently, we have more than 50 peripheral IP blocks developed and ported. Our IP portfolio covers a variety of baseline IPs and application IPs. We are a full range ASIC design service provider. Our IP category library and applications are listed below: 5. INFORMATION ON OUR GROUP (CONT’D) AudioNideo IPs  VOIP  WiFi  MP3  DVD recorder  Set-Top Box  Image Processor  Multimedia server  PMP  DAC  ~  ~  ~  ~  ~  ~  ~  ~  ADC  ~  ~  ~  ~  ~  ~  ~  ~  Audio Codec  ~  ~  ~  ~  ~  ~  Voice Codec  ~  ~  ~  ~  ~  DVI  ~  ~  ~  Power Manaqement  lDO Voltage regulator  ~  ~  ~  ~  ~  ~  ~  DC/DC converter  ~  ~  ~  ~  ~  ~  Power on Reset  ~  ~  ~  ~  BandGap  ~  ~  ~  ~  ~  ~  Connectivitv  802.11a/b/g/n AFE  ~  ~  ~  PClxl PCle  ~  ~  SATA  ~  ~  ~  ~  ~  Ethernet 10/100  ~  ~  ~  ~  ~  FireWire 1394  ~  ~  ~  USB2.0  ~  ~  ~  ~  ~  ~  ~  ~  DDR  ~  ~  PATA  ~  ~  ~  1/0  Programmable CUP 1/0  ~  ~  ~  ~  ~  ~  HSTU SSTl  ~  ~  lVDS  ~  ~  ~  ~  ~  ~  CE-ATAlMMC  ~  Universal Cardbus  ~  MISC  RTC  ~  ~  ~  ~  ~  ~  ~  Pll  ~  ~  ~  ~  ~  ~  ~  ~  High Speed datapath KEYWARE  ~  ~  ~  ~  ~  ~  ~  ~  ROM  ~  ~  ~  ~  ~  ~  ~  ~  SRAM  ~  ~  ~  ~  ~  ~  ~  ~  RF  ~  ~  ~  ~  ~  ~  ~  ~  High Density standard cells  ~  ~  ~  ~  ~  ~  ~  ~  Dll  ~  ~  CPU  ARM926EJS  ~  ~  ~  ~  ~  ~  ~  ~  ARM946ES  ~  ~  ~  ~  ~  ~  ~  ~  High Speed ARM926EJS  ~  ~  ~  ~  ~  ~  ~  ~  low power ARM926EJS  ~  ~  ~  ~  ~  ~
Figure 1 .. IP Category Library and Application 5. INFORMATION ON OUR GROUP (CONT’Dj There are 4 components of revenue received for our services, which comprises non-recurring engineering (“NRE”) charges, IP licensing fee, royalty fee and sales of chips. • NRE charges are one time charges for the engineering effort in designing the chips or IP. Customers would have to pay a higher non-recurring engineering charges if there is customisation or if they require certain specification to the design of the chips;
• IP licensing fee is a licensing fee charged for the usage of the IPs in customer designs;
• Royalty fee is a recurring income paid by customers to our Group for every chip manufactured using the IP licensed from us; and
• Sales of chips are the sales of completed chips in the form of packaged chips or wafer.

The diversified revenue model helps our Group to ensure business sustainability and reduces dependency on any single source of income. One of the key distinctive features of our Group’s services in comparison with the services provided by our competitors, that would attract repeat orders from customers is that our strategic partnership with Silterra allows us to have preferential access to Silterra’s foundry capacity, providing us a short turnaround time and on-time delivery. Additionally, given the lower engineering and premise rental cost in Malaysia, we can generally offer a better price to our customers around the world as compared to our competitors from Taiwan, Singapore and USA. The rest of this page is intentionally left blank

5. INFORMATION ON OUR GROUP (CONT’D) 5.4.2 Design and Production Flow Design Flow Technology and Tool Selection  Functional specifications, vendor data, performance requirements, organization  Review  requirements
Pre-layout  PDR  Review
..~_p_a_rt_i_ti_o_n_in_g_~ .. ‘,_ ASIC Specification(s)) tests, detailed ~.~______ “”‘~_device specification Production Flow ASIC design and
Bare die, packaged Engineering & flightUnusable partsparts parts Figure 2: ASIC Design Flow Figure 2 above illustrates the entire design and production flow for ASIC and SoC of Key ASIC. The ASIC design flow is the major engineering development for our Group and will be the design environment platform for all products in our future development. The flow is illustrated in a simple and rough chronological, single-threaded sequence. 5. INFORMATION ON OUR GROUP (CONT’D)
The following is the description of the major process of the above ASIC flow: Partitioning is the process to carve out the correct part of the system for implementation as an ASIC. The system architects and ASIC designers will perform general partitioning from the time system level specifications are laid out. Test and performance requirements, global device specifications such as testability specification and functional specification must be taken into account during the partitioning process. In this process, the system architects will do the system level performance verification to verify the logic partitioning. The ASIC implementation delivers a complete ASIC design and associates the design with complete verification test programs. For ASIC design, the primary emphasis is on the optimum use of resources to satisfy specific performance, reliability and cost requirements. The ASIC implementation has to come along with its verification and testability analysis. The verification including simulation and test vector generation are the most important events of an ASIC implementation. The ASIC implementation methodology focuses on first-pass successful silicon. The first-pass successful silicon would mean an ASIC device built from the first preliminary design review (“PDR”) and critical design review will work correctly in its system and require no redesigning. Physical layout is ASIC design at the final level. The ultimate result of this design work are fabrication masks used to build ASIC parts. Physical layout is done through place and route using foundry provided physical libraries after the PDR sign-off. After completing the layout, the designers review the back-annotated resistance and capacitance values arising from the inter-connects in the physical layout. These numbers reflect reasonable estimates of the final design’s worst case and best case performance. This review consists of post-layout simulation and path analysis to make sure no significant changes in functional and performance have occurred because of layout. The manufacturing process is to produce ASIC dice assembled into packages. The manufacturing process consists of 3 phases which comprise wafer fabrication, wafer probing using automated test equipment and prober, and assembly process by separating dice from wafer and assemble into package unit. We do not have wafer fabrication facilities, hence we outsource our fabrication processes to Silterra, our foundry partner. The wafer fabrication process requires approximately 6 to 10 weeks for completion. Testing and characterisation ensures that the manufactured parts meet the goals of the ASIC design. The ASIC chips have to meet the testing and characterisation outlined in the contract. The characterisation focuses on electrical, performance and power characteristic of the chips. Currently, the physical test and packaging of the chips are also outsourced to our test and packaging partner, ASAT Holdings Limited. Part acceptance applies quality and reliability criterion to parts delivered for prototyping and engineering samples. This process will screen out devices that show potentially serious problems. Upon completion of this process, the final end product will be delivered to the customers. 5. INFORMATION ON OUR GROUP (eONT’D) 5.4.3 Principal Market 5.4.4
B0 Fabless ASIC/IC I 10M COT ~~~~~d,etSi~gn~COQm~p~a~n~ie~Scm~m!;m~i~~mI3’~~~~I mJ.-•-. .• ,—–. –n I Foundry Figure 3: Market segment Figure 3 above describes the market segments in our industry. Semiconductor or IC is a global business in nature. Companies in the semiconductor market compete based on technology and selling capability. According to the Directors of Key ASIC, most of the fabless design companies in the world today design mainly ASSP products. However, there are only limited fabless design companies, including our Group, that have its own technologies and capabilities to design a process technology specifically into a foundy process directly using their own IP, PDK and design flow. Usually, our customers are the fabless design houses, IDM, system ASIC companies and COT companies. We have made our mark with some leading customers in USA, Europe, Taiwan and Malaysia. Our services are usually targeted at consumer electronic and communication market such as PMP, MP3, digital audio player, set top box, digital TV, digital media broadcast, digital imaging, mobile phones and wireless network. Moving forward, we will focus on capturing turnkey design businesses in China, Japan and Korea. Technology Used Our Group’s primary technology is the KeyPlatform for ASIC and SoC design-to-manufacture that aims to reduce customer design time and allow first time silicon success. KeyPlatform is a technology that comprises our design methodology and software used, coupled with our own IPs developed. The platform provides a high performance ARM-based CPU platform with CPU core and memory blocks, for integration of domain specific IP blocks to design a specific SoC qUickly. A wide variety of mixed analogue digitallP blocks, memory blocks of different sizes and speed, high quality audio and voice codec, and peripheral interfaces are available for quick integration of a chip. The platform also consists of a wide selection of silicon proven interfaces such as USB2.0, IEEE 1394, ETHERNET, PCle, and many others. The system and circuit design steps are aided by the use of EDA tools. These EDA tools are software tools used by our designers for the development of chips and systems. The EDA tools allow the creation and simulation of the chip functionalities and performance. The usage period of the EDA tools are governed by their respective licensing terms. 5. INFORMATION ON OUR GROUP (CONT’D) 5.4.5
Mode of Marketing Marketing of our services comprises design introduction to potential customers, discussions with customers on the application of the chips and obtaining system designs contract. We would normally require an upfront commitment from our customers before we commence any design work. As part of our sales strategy, we would also design for our customers based on a memorandum of understanding signed in the effort to attract repeat orders from customers by offering lower wafer cost. We are able to offer lower wafer cost as compared to our competitors due to our strategic partnership with Silterra allowing us to have preferential access to Silterra’s foundry capacity as well as the lower engineering and premise rental cost in Malaysia. For those customers with large volume demand, we would design without collecting a design fee upfront as the fees are usually incorporated into the wafer price. Our direct sales team is headed by Mr. Chan Woo Nam, our designated Vice­President of Strategic Accounts pursuant to a Management Agreement dated 1 January 2006 to which we have appointed Key ASIC Inc. to sell and market our services in all countries, other than Malaysia, subject to us also having the rights to continue marketing our own services. Key ASIC Inc. has appointed Mr. Chan Woo Nam as a representative to act as liaison with our Group and shall maintain a dedicated team of sales, marketing and technical support personnel in the region to visit prospective customers and provide timely feedback to us on the technical requirements of customers in relation to the product and sales requirements and engage customers to secure business with our Group. Key ASIC Inc. will facilitate the conclusion of definitive agreements to be signed by us directly with customers. The strength of our sales team is also coupled with the experiences, business relationship and network of some of our Directors, namely Benny T. Hu and Eg Kah Yee, to which both are very instrumental and capable in assisting our Group in bringing in businesses. Our marketing strategy is not just to target our services to fabless design houses, but also the 10M, system ASIC companies and COT companies. We intend to focus our marketing effort towards the consumer electronics and communication industry with the intention of customising and developing of ASIC and SoC for their applications. We will focus on high end turnkey market where most design houses do not have the capability in designing. Designs such as audio/video or multimedia communication and networking are areas of our focus. We market our services through various platforms including technology forums, seminars, website, electronic mails and participation in conferences and trade shows. In addition, we also organise joint marketing programmes with foundries, IP partners, design service partners and IC component distributors. Our sales strategy is to have high volume production chips to achieve economies of scale and to provide our Group with sizeable recurring revenues. We will capture the next version of high volume production chips and optimise their designs to have higher performance, lower power consumption and small die size, hence giving the chips a better price/performance ratio. We will maintain a strong team of system designers with broad chip design knowledge to promote and support our services. 5. INFORMATION ON OUR GROUP (CONT’D) 5.4.6 Quality Control Procedures In order to provide high quality IPs and ASIC design services, our Group has established distinct quality policies to achieve its goals through continuous improvements as follows: (i) To ensure precise efficiency by strictly obeying the standard operating procedures;
(ii) To constantly improve total quality by implementing quality management procedures;

(iii) To stay ahead of customers’ needs by constantly scanning the global market for new development; and (iv) To maintain technological lead by providing an aggressive commitment to R&D. We practice the following quality control and management procedures as described below: (a) IP Sign-Off Process
5. INFORMATION ON OUR GROUP (CONT’D) The above diagram illustrates our IP sign-off procedures. The quality control begins at the initial checkpoint when IP vendors provide the design database, design documentation and characterisation results to our Group through our secure File Transfer Protocol (“FTP”) or Virtual Private Network (“VPNlJ). Subsequently, our design engineers will download the design database and documentation, and conduct a design review based on a standard review design checklist. Once our design engineers are satisfied that the design meets all the criteria of the checklist, they will accept the design checklist and provide all their feedback to the IP vendors if there is any design error. Thereafter, the IP vendors would have to review the criteria of the checklist and the feedback, and provide design fixes based on the feedback. The design review will begin at the initial checkpoint again once the design error is fixed. However, if there is no design issue found, the design is considered as complete and our design engineer will sign-off the design. (b) Design Release Process Pre-Tape-out During Tape-out Post Tape-out Silterra provides -Myfab & MyFTP accounts -Foundry service Manual -Standard process Technology Design Support Documents in MyFab  ,  II’  Customer Action -Download latest spees from Myfab -Perform DRC/LVS with latest spes -Complete CAD form, Device information Form at MyFab -Generate metal dummy fill -Inform Silterra of tape-out
t Customer provides Customer Action-GDSII database -Computer Automated Design -Perform E-jobview form, Device info Form -Email approval for mask -DRC summary & report File writing. -Purchase order & purchase requisition form for proto lot start + Silterra Action Silterra Action -Notify mask shop for mask writing• GOSH database, Computer Automated Design Form, Device -Start proto lot before first information Form check reticles in -DRC, IP screen check -Inform customer of proto -Optical Proximity Correction, fab-out date frame generation -Process proto lot -Release database to mask shop for active dummy fill and -Provide electrical test fracturing summary & ship proto lot -Arrange E-jobview for customer • -Provide electrical test summary &ship proto lot 5. INFORMATION ON OUR GROUP (CONT’D) The above diagram describes our quality control procedure before releasing our designs to our foundry partner, Silterra. As all our designs i.e the GDS II files are transferred via the internet, a secured private FTP account, namely MyFab and MyFTP accounts are created by Silterra specifically for Key ASIC in order to ensure there are no unauthorised access to the database. At the same time, Silterra will provide their Foundry Service Manual and Standard Process Technology Design Support Documents via MyFab. Our design engineers will download all the fabrication device forms and latest process fabrication design rules and scripts from MyFab. This is to ensure that our design engineers are able to perform a final design verification using Silterra’s provided rules and scripts with minimum design error. Once the design is completed, our design engineers will transfer the complete GDS II database to Silterra though the secure MyFTP account. Subsequently, Silterra will review and check the design database and the device forms to ensure that the fabrication process conform to quality standards and design specification. Once review is completed, Silterra will arrange the E­Jobview for Key ASIC. Our design engineers will then review the E­Jobview to ensure that the fabrication masking layers do not have any issue. Our design engineers will communicate their approval to Silterra via electronic mail to start mask writing process. Lastly, Silterra will kick-off the fabrication process. (c) Design Back-up System Apart from all the quality control procedures, in the event of any catastrophe like earthquake or fire, or business interruption due to the cut of electrical supply, our Group’s internal design database is protected through an external design back-up system. Our internal design database is backed-up on a weekly basis to an off-site external storage. 5.4.7 Research and Development (a) R&D Policy and Focus We are committed to continuously carry out R&D efforts by keeping abreast with market developments and trends. We believe that continuous R&D is crucial in order to compete effectively. Our Group conducts research in its core area of development such as commercialising silicon IPs, designing ASIC and SoC (including prototype) with high performance, low power consumption and small die size, developing turnkey services including back-end testing and fabrication manufacturing technology and verification. We base our engineering development using the following strategies: (a) internal R&D utilising our own resources; and
(b) working in partnership with the leading players in different sectors, through design collaboration or joint ventures.

5. INFORMATION ON OUR GROUP (CONT’D)
Figure 4: SoC development phases Figure 4 above illustrates our R&D engineering development plan that comes in 3 phases. The first phase is to build the wireless and consumer end analogue and digital IPs, design and testing capabilities. The phase 2 development is to work on the high performance and low power consumption microprocessors that serve in the wireless and personal electronics segment. The phase 3 focus is to develop more SoC products such as VoIP, Wi-FI, set-top box and MP3. The complete engineering competency development is planned across 3 years starting from 2006. Our main focus in the near term is to provide superior design flow and optimisation technology to quickly and cost-effectively meet SoC requirements for high-volume. high performance, and low cost consumer applications. Our R&D engineering development roadmap is tightly mapped against Silterra’s process roadmap. This is to ensure that we are able to provide design expertise and vaiidate the new logic and mixed signal process technologies into Siiterra. Currently, the technologies available under Silterra include various 0.181-1, 0.161-1 and 0.131-1 technologies. 0.111-1 is currently under development and is scheduled to be avaiiable by first half of 2008. 5. INFORMATION ON OUR GROUP (CONT’D)
(b)
(c)

R&D Facilities and Technical Personnel As an MSC status company, we have R&D offices located at Cyberjaya and Petaling Jaya. This Malaysian-based R&D facility will support its worldwide sales. There are 16 designers who are involved in our R&D activities. The R&D engineering team is headed by Mr. Lai Kok Keong. Our R&D engineers have multiple years of design experience and some of them have worked with leading semiconductor companies around the world including but not limited to Intel Corporation, Agilent Technologies Ltd, Altera Corporation, Avago Technologies Ltd and National Semiconductor Sdn Bhd. The design capabilities of our engineering team include the following: • ASIC and SoC design experience for various technology nodes including but not limited to 0.25~, 0.18~. 0.16~. 0.13~, 0.11~, 0.09~ and 0.065~ process technologies;
• High performance design including 3.0 GHz CPU in the past;
• Low power design for mobile and hand held devices such as cellular phones, MP3, PMP and hand-held games;
• CMOS and SOl technology design experience;
• Complete front to back design capability starting from specification, RTL, gate, layout to GDS II;
• Advanced design methodology including ASIC design flow, semi-custom and custom design flow; and
• Ability to design all IPs in the SoC including CPU, Memory, I/O and Analogue.

Our management plans to expand the R&D team in the next 2 years. The total number of R&D staff is expected to increase to 45 personnel by the FYE 2009. FYE 2007 2008 2009 Total R&D staff 16 34 45 Investment in R&D We did not incur any R&D cost during the year of our incorporation in 2005. However in the FYE 2006 and the 9-month FPE 2007, our total investments in R&D were RM2.07 million and RM2.44 million respectively which representing about 4.1 % and 8.5% of our total turnover for the same year/period. We have budgeted an annual R&D expenditure of approximately 24% of our annual consolidated revenue from the FYE 2008 up to the FYE 2009, to finance our R&D activities. 5. INFORMATION ON OUR GROUP (CONT’D) (d) We will continue to invest heavily in our R&D activities and have allocated RM36 million from our listing proceeds towards R&D. Please refer to Section 3.8 of this Prospectus for further information on the proceeds used for R&D activities. R&D Milestones 2006: Our engineers’ main focus was improving Key ASIC design flow, circuit optimisation technology and enriching our analogue IPs. Our R&D team has developed a set of analogue IPs and general CPU based on various 0.18~, 0.16~ and 0.13~ technologies. Our ARM 926/946 CPUs developed are characterised both in Silterra’s 0.18~ and 0.13~ process technology. A number of consumer and electronic applications have also been developed for customers namely, MP3, DVD, PMP Wi-Fi, WiMAX and VoIP. We have also developed a design flow that will automate the shrinking process. 2007: Our R&D engineers will continue to focus on porting IPs and plan to complete porting of all defined IPs on Silterra’s 0.13~ technology. Our R&D engineers have developed a prototype high performance ARM926 CPU at 333MHz on Silterra’s 0.13~ technology as compared to the ordinary ARM926 CPU at 250MHz. We will focus our engineering expertise on CMOS 0.16~, 0.13~, 0.11 ~ and low power process and will work closely with Silterra to develop and fine tune the 0.11 ~ device model in line with Silterra’s 0.11 ~ roadmap. 2008: New IPs development focus will be on 0.11 ~ and 0.09~ process technologies. In addition, our Group will also expand our application platforms and will also be developing some new IP needs. We will also work on low power CPU, KeyWare, low power custom memory and optimising circuit techniques to provide customers with complete low power solutions. 2009: We will work closely with Silterra to develop the 0.065~ test chip and fine tune the fabrication process and device modelling. Developing a new methodology to support the use of multiple cores in a single SoC will also be necessary. Design for manufacturing will be one of our future focuses that we are looking into incorporating into our design flow. 5. INFORMATION ON OUR GROUP (CONT’D)
5.4.8 Competitive Strengths and Advantages We believe that our competitive strengths and advantages lie in the ability of our technical team to design high performance, low power consumption and smaller size chips which includes CPU, DSP and graphic design. Our strengths in the above areas are, to a large extent, achieved through the following: (i) Experienced management team and strong technical personnel Our Group consists of an experienced management team coupled with an experienced Board of Directors who have helped define the product roadmap for the development of new chip design ideas for ASIC and SoC. Our management team and Board of Directors have many years of design experience at some of the world’s leading semiconductor companies which includes Intel Corporation, Agilent Technologies Ltd, Synopsys Inc., Altera Corporation, Avago Technologies Ltd and National Semiconductor Sdn Bhd. As a result, our Group is able to leverage on the wide network of our experienced management team. Please refer to Sections 7.1 and 7.3 for more details on our Director’s and key management profile. One distinct competitive advantage that our Group possesses over other design companies is that our technical personnel has the technical expertise in the system architecture design and RTL to netlist design, and the ability to optimise the design to maximise the performance, reduce power and die size at a cheaper cost. Most design service companies provide place and route service, and are not capable of providing architecture level and RTL to netlist design service. Our experienced team of designers has consistently delivered many high performance CPUs, DSP and graphics designs and many communication and consumer SoC. High performance and low power is the core competency of our design team. (ii) Strong strategic partnership with foundry players In Malaysia, there are only 2 process foundries, namely X-FAB Sarawak Sdn Bhd (formerly known as 1sf Silicon (Malaysia) Sdn Bhd) and Silterra. Silterra is a growing process foundry service provider. It offers CMOS logic, high voltage and mixed-signal/radio frequency process technologies to customers of all sizes worldwide including many top-tier semiconductor companies. Silterra is the first foundry partner to our Group as we have a complete set of IPs and design capability targeting products that are suitable for Silterra’s process technologies. This is also an important partnership to the foundry as the foundry would require chips designed into its foundry process technologies so that they can get wafer manufacturing business. Our Group has developed and ported our IPs on Silterra’s O.181J, O.161J and O.131J technologies. At the same time, we have outsourced our manufacturing process to Silterra. 5. INFORMATION ON OUR GROUP (CONT’D) (iii) (Iv) Having formed a strong strategic partnership with Silterra, our Group is able to provide customers with a more complete solution by having a one-stop design-to-manufacture service as compared to many advanced players in Malaysia. Our Group has preferential access to Silterra’s foundry capacity which guarantees us short turn around time and on-time delivery, even for small to moderate volumes. Rich set of IP portfolio Our Group currently has more than 50 different peripheral IPs developed and ported that are silicon proven, targeting the consumer electronics and communication segment. Through our KeylP Service, our Group offers customers the ability to license IPs from our pool of mixed-signal and digitallP, including interfaces, IPs blocks, CPU and DSP cores. Our Group has developed a complete set of IPs for platform of VoIP, Wi-Fi, MP3, DVD, set top box, image processor, multimedia server and PMP. The key differentiator of our Group is the ability to develop a set of datapath IP components such as various arithmetic integer adders, barrier shifters, incrementer and decrementer for optimisation of speed, power and die size of the ASIC and SoC. For instance, KeyWare is a set of various IP blocks developed by our Group optimised for performance and power. Possess high-end SoC designs A SoC design incorporates a whole system on a single chip, containing CPU processors, embedded memory, peripherals, and other system blocks. Combining SoC modules with various design styles on a single chip will dramatically increase the complexity of the following areas: • Die size reduction
• Functional verification
• Power reduction
• Physical verification
• Performance improvement

Yet, as complexity increases, the time to get these devices to market continues to decrease. Producing these highly complex SoC designs requires an experienced design team to employ highly efficient design methodology and high end SoC modules (CPUs, embedded memory peripherals, etc) to overcome the issues that arise in the above mentioned areas. Our Group is able to provide smaller die size, lower power and higher performance SoC modules such as CPU and other peripheral IPs to develop the complex SoC designs. Furthermore, the engineering group is experienced in EDA design methodology development that is able to reduce the design time and design iterations. 5. INFORMATION ON OUR GROUP (CONT’Dj (v) Ability to design high-end CPU for consumer electronics Our Group is one of the few IC design service companies in the world that possesses high end CPU, DSP, memory design experience and capability. Currently, we have developed high performance ARM946E-S CPU which is based on ARM architecture that is capable of operating at 200MHz internal clock speed, which is 18% faster than the original ARM946E-S that normally operates at 170MHz. On the power consumption part, we are able to achieve approximately 7% lower at 0.84uW/MHz than the original ARM946E­S which was running at 0.90 uW/MHz. CPUlDSP and memory is the critical part of any SoC. With the continuous push for performance, low power consumption and smaller die size, optimisation of CPU speed and reduction of power becomes a unique competitive edge that we possess as compared to many design houses in the world. (vi) One-stop solution service centre Our Group offers our customers a single point of contact for our high­end SoC integration starting from high-level marketing specifications down to tape-out to a foundry to fully qualify ASIC and SoC products. Our Group handles the whole design chain and adds key value to the stages of the development to ensure successful delivery of the end product. With the strategic partnerships of our foundry partners and testing houses, we are able to handle all intermediate stages of the design efficiently and ensure the overall performance and quality of the SoC is maintained. This has definitely provided us with a more complete solution to customers than most advanced players. 5.4.9 Key Milestones, Awards and Recognition
November 2005 Formed partnership with Silterra March 2006 Developed and ported our first set of IPs on the 0.18J,J process technology of Silterra April 2006 Announced our design-to-manufacture services for portable and consumer applications Granted MSC status by MdeC May 2006 Successfully tape-out high performance, low power consumption ARM946E-S CPU September 2006 Developed and ported our first set of IP on the 0.13J,J process technology of Silterra December 2006 Delivered the 0.13J,J PDK validation to Silterra February 2007 Tape-out SkyMedi products June 2007 Incorporation of KASSa 5. INFORMATION ON OUR GROUP (CONT’D)

July 2007 August 2007 September 2007 October 2007  Tape-out Gigabit Ethernet product that has smaller die size and faster speed. Proven high speed and low power techniques in customer product. Successfully delivered the Silterra C13G CUP 1/0 IPs Post-silicon verified 0.13u ARM946E-S 30% better performance than standard specifications. ARM946E-S operates at 270MHz Completed the Silterra CL130G PDK validation. Tape-out customer from USA (Intellasys) Place & Route project within 7 days.
5.4.10 Interruptions to Business We did not experience any disruption in our business which has a significant effect on our operations for the 12 months period prior to the date of this Prospectus. 5.4.11 Intellectual Properties Save as disclosed below, we do not own any other registered brand names, trademarks or licenses: (i) Copyright of all our peripherals IPs; and
(ii) License over our peripherals IPs and EDA tools

5.4.12 Principal Place of Business The principal place of business of our Group as well as our core R&D personnel and activities are located at Lot 6.03, Level 6, KPMG Tower, No.8 First Avenue, Bandar Utama, 47800 Petaling Jaya, Selangor Darul Ehsan and Unit No.: C207, 2nd Floor, Block No. 3440 (Enterprise Building 1) Cyberjaya respectively. 5. INFORMATION ON OUR GROUP (CONT’D) 5.5 MAJOR SUPPLIERS Our major suppliers for the past 2 FYE 2006 and the 9-month FPE 2007 which contributes 10% or more of our Group’s total purchases are set out below: <–•••••••% of purchases ——–> FYE FYE FPESupplier Country Length of relationship 2005 2006 2007 KAL Taiwan Since September 2005 66.05% 17.74% Key ASIC Inc USA Since January 2006 33.95% 61.90% Global Grand Taiwan Since October 2006 16.05%Group Ltd We are, to a certain extent, dependent on our current suppliers for provision of EDA design tools as well as the development, design and licensing of certain IPs. We have entered into Software License Agreement and Technology License Agreement with KAL whereby we were granted non-exclusive rights to install the software and to use or authorize use of the software and to use certain technology provided by KAL. Pursuant to the Outsourcing Agreement with KAL, KAL shall assists in developing, design and licensing certain IPs to us. We have also entered into an Outsourcing Agreement with KA Inc. whereby we are licensed to use certain ported IPs of KA Inc. These agreements were entered into as we have limited resources to develop and design certain IPs required in view that we were then only a start-up company. Further, it is also very expensive to develop our own EDA tools internally. Outsourcing is an industry norm in the semiconductor industry due to the high capital and labour cost involved and increasing competition which drive companies to reduce costs and shorten time-to-market. Also, our industry entails high expertise to operate and the lack of competitive local IC design support as well as lack of IC design talent both in quantity and experience, has prompted us to outsource our design facilities to overseas expertise. It is also part of our business strategy to adopt the outsourcing model as and when required. Going forward, the outsourcing of IP development and design is expected to decline as the basic IPs required for design engagement have been substantially developed in the FYE 2006 and most of these IPs can be re-used for many years. This is because the algorithm design of these IPs do not change in principle. Nevertheless, we may outsource certain IP development and design to third parties as and when the need arises and ensure that the arrangements are in the best interest of our Group. Meanwhile, we will continue to recruit experienced and technical personnel. We have also taken continuous efforts to strengthen and enhance our relationships with our existing outsourcing partners and also build new relationships. This would provide us a wider range of outsourcing facilities and hence, ensure that our operations continue to run smoothly. 5. INFORMATION ON OUR GROUP (CONT’D)
5.6 MAJOR CUSTOMERS Our major customers for the past 2 FYE 2006 and 9-month FPE 2007 which contributes 10% or more of our Group’s total revenue are set out below: <——-% of revenue –_.-.> FYE FYE FPECustomer Country Length of relationship 2005 2006 2007 Silterra Malaysia Since March 2006 87.32% 84.16% Global Grand Taiwan Since October 2006 11.53%Group Ltd MTek Limited Taiwan Since September 2007 12.30% Our Group is, to a certain extent, dependent on Silterra as about 84% of our Group’s revenue for the 9-month FPE 2007 is from sales to Silterra, of which 76% revenue from licensing and porting of IP designed specifically for Silterra’s semiconductor manufacturing process technology and 8% revenue from commission earned for introducing about half of the end customers to Silterra. Silterra is a process foundry in Malaysia. However, due to the nature of the semiconductor industry, it is a norm for pure IC design houses to form strategic partnership with foundries and subcontract its manufacturing work to pure foundries. As we have the ability to have our technology designed specifically into Silterra’s process technologies and as a result of that, Silterra can get wafer manufacturing business, this can be seen as an inter­dependent relationship that can be beneficial to both parties. This tight collaboration between ASIC design service companies and the foundries can be seen in successful business models such as Faraday Technology Corporation, a design service company listed in Taipei Stock Exchange collaborating with United Microelectronics Corporation, a world leading semiconductor foundry in Taiwan, as well as Global Unichip Corporation, the second largest ASIC design service company collaborating with its major shareholder, TSMC, a leading foundry player, both located in Taiwan. Emulating these successful business models, we have signed a Foundry Service Sales Representative Agreement with Silterra, whereby we are appointed as marketing representative for Silterra in certain countries, and we will be paid a commission for acquiring the sale of silicon wafers fabricated by Silterra. We have also entered into IP Porting Services Agreement and CPU Agreement with Silterra, whereby we shall provide design services and license of IP to Silterra whilst Silterra shall undertake to manufacture the chips designed by our Group containing the ported IP using only manufacturing process specified in such agreements. Please refer to Sections 4.2.7 and 5.4.1 for additional information on the relationship between Silterra and the Group. 5. INFORMATION ON OUR GROUP (CONT’D) 5.7 FUTURE PLANS, STRATEGIES AND GROWTH PROSPECTS Our Group’s mission is to provide customers with SoC platforms of various applications to reduce the design time and enable first time silicon success. Wireless, high performance and low power consumption is the key to our future IC designs. We aspire to maintain our position as the leading IC designer in Malaysia. To this end, we will build on our current strengths and competitive advantages and further explore new opportunities for market expansion. In this regard, the action plan put in place by us to ensure continuing business growth includes the following: 5.7.1 R&D Engineering Development Plan Our engineering development roadmap is tightly mapped against Silterra’s process roadmap. This is to ensure that we are able to provide the design expertise and validate the new logic and mixed signal process technologies into Silterra. Figure 5 below illustrates the technology roadmap of Silterra. Logic&MixSignal ~~~ • 020304 01020304 01020304 Cl1EOMR 1B133V CL 120VT 12125,33 CL22JG 2!5133V
Cl1EOGHS 1B~V

CL 1EOLP 1B133V

Note Lett edge of box IS start of risk produ::tl0n CL 130YT lsthe hgh Vi option Figure 5-Silterra’s process technology roadmap Currently, the technologies available under Silterra include various 0.181.1, 0.161.1 and 0.131.1 technologies. 0.111.1 and 0.091.1 technologies are currently under development and are scheduled to be available in 2008. The above diagram shows that the process technology is shrinking in size. We have mapped our R&D engineering roadmap into Silterra’s process roadmap as illustrated in Figure 6 below. In the near term, our plan is to provide superior design flow and optimisation technology to quickly and cost-effectively meet SoC requirements for high volume, high performance and low cost consumer applications. 5. INFORMATION ON OUR GROUP (CONT’D) In 2007, our R&D engineers’ main focus is to improve the ASIC design flow and to improve product testing and characterisation. We will continue to focus on porting IPs and plan to complete porting of all defined IPs on Silterra’s 0.131J technology. Our R&D engineers are also working on designing a higher performance ARM926 CPU at a higher speed of 333MHz on Silterra’s 0.131J technology as compared to the ordinary base performance ARM926 CPU at a speed of 250MHz. Programmable 110 and CUP 110 are also in the midst of being developed currently. Our engineers will work closely with Silterra to improve the process by using TSMC’s process as a benchmark. In 2008, our engineering design techniques will focus on porting and characterising eXisting IP’s into Silterra’s 0.111J and 0.091J technologies depending on Silterra’s process availability. We intend to work closely with Silterra to develop the 0.111J and 0.091J test chips and fine tune the fabrication process by using other foundries’ process as a benchmark. In addition, our Group will also expand our application platforms and will also be developing more specific IP application needs. 2006 2007 2008 •i” General CPUs for I” General CPUs for I” General CPUs for I • •• 1 consumer end and I consumer end and I consumer end and I mobile products I mobile products in I mobile products in I ~–r—Specrtrca-narog—–T——Cfifte-re-nff60mlrV—-I——-aiffereiilTounary—-l • • 1 IPs for the I” More specific I” More specific I • 1 consumer end and I analog IPs for the I analog IPs for the I 1 mobile products. I consumer end and I consumer end and I• +-v”—~e~~~nnc<;—–.——-rnotntelJnJd~s:—-i——lnTabMe-PTo1tacts~—i 1 (ASIC) I” Design service I” Design service I • I” High performance I (SoC, ASIC) I (RTL coding & I 1 CPU for consumer I” High performance validation, SoC, • ~——~R~a~~He————-(7p{j~~~e6flS~FAef–I——-A~fG, J 1 products I end and mobile I” Low Power CPU I • I” High performance I products I for consumer end I I (HP) KEYWARE I” More HP I and mobile I •
l——~ev~~t——-J——-~~~~———I——~~o~———–J ” Product testing I development I” Low power I 1 and packaging I” Product testing I KEYWARE I 1 capability I and packaging I development I ~…………,L_~ C~J_PI9P_~§§ 1——-p~gpllitY——–I–~—-S9-C-~I9slyQt——-1 1 migration I” Key Platform I testing and I • • 1 procedures I development I packaging I • I” Target process “Target process capability • •~——-<-~~~~~~)18G——–~——-i?~I~~!~~~J6~~-~2—–:–v:—-~~*~~~~~~nf——-: o O.16G I 0 O.16G I” Target process I •• 1 0 O.16LP I 0 O.13G I (S’lt ITSMC/SM I 1 0 O.13G 0 O.13HVT I erra o O.13HVT I 0 O.09G I IC) I +—————————.—————————-I——–~—IT.’3C;——-1 1I I 0 O.13MVT/LP I 1 0 O.09G II 0 O.065G I –‘•Figure Ii -R&D Engineering Development Plan I Company No.: 707082-M I 5. INFORMATION ON OUR GROUP (CONT’Dj 5.8 LANDED PROPERTY The landed properties rented by our Group are as follows: Rental Ownerl Management LandI payable Postal address Company Existing use Built-up area #CF per month Duration of tenancy sqft RM
Lot 6.03 KPMG Tower Bandar Utama City Sdn Bhd Corporate 6,813 square feet Issued on 25,889 3 years (commencing from 1 July 2007) No.8, First Avenue (Company No. 268323-H) office 17.07.06 Bandar Utama 47800 Petaling Jaya Selangor Darul Ehsan Unit No.: C207, 2nd Floor, Setia Haruman Sdn Bhd Corporate 1,133 square feet Issued on 3,059 2 years (commencing from 1 Block No. 3440 (Enterprise (Company No. 425154-U) Office 19.08.02 September 2007) with an option to Building 1) renew for a further 1 year Cyberjaya Notes: # CF represents cerlificate offitness for occupation. As far as our Directors are aware, there has been no material non-compliance with any laws, rules and building regulations in relation to the use of the above properties rented by our Group. We do not own any property and we have not acquired any property since the date of our incorporation up to and including the date of this Prospectus. 63
6. INDUSTRY OVERVIEW
6.1 OVERVIEW
6.1.1
Overview of the Malaysian Economy Malaysia’s 50 years of nationhood marks another milestone in its economic development. Upon independence, the nation was highly reliant on tin and rubber and more than half of the population were in poverty. Today, Malaysia is a broad-based and diversified economy. The Government’s far-sighted and pro-business policies were instrumental in the transformation of the economy. Towards this goal, economic management in 2007 is focused on enhancing domestic resilience to facilitate growth and development as envisaged in the National Mission, which commits to continuing the structural transformation towards becoming a developed nation by 2020. In this context, initiatives were taken to Iiberalise the Foreign Investment Committee guidelines, reduce corporate tax to 26% in 2008 through special incentives, strengthening of the human capital development and improving the public transportation and delivery systems. With these measures and initiatives, all sectors of the economy will continue to expand. In an environment of low inflation and unemployment, high savings, favourable exchange rate as well as strong current account balance, the macroeconomic fundamentals of the country remain strong. The Malaysian economy is expected to expand strongly by 6.0% in 2007. The services sector, with an anticipated of 9.0% will continue to be the major contibutor to real GOP on the back of robust activities in intermediate services comprising finance and insurance, real estate and business services, transport and storage as well as the communications industry. The manufacturing sector is expected to pick up gradually and expand by 3.1 %, following the anticipated recovery in global electronics demand in the second half. On the demand side, growth will be driven by resilient public and private sector expenditure, flowing stronger consumer sentiment, business confidence and higher Government spending. Nominal gross national product is estimated to increase by 9.4% to RM607,212 million, with per capita income increasing by 7.2% to RM22,345 (2006: 9.9%; RM20,841). In terms of Purchasing Power Parity (UPPP”), per capita income is expected to increase by 13.9% to reach US013,289 in 2007 (2006: 13.0%; US011,663). The Malaysian economy is expected to register robust growth in 2008, with real GOP expanding between 6.0% and 6.5%. This translates to a 6.8% growth in nominal per capita income, rising from RM22,345 in 2007 to RM23,864 in 2008 or in PPP terms from US013,289 to US014,206. With an unemployment rate of 3.3%, the Malaysian economy will continue to operate under full employment. In tandem with the Government’s efforts to ensure fiscal sustainability, the fiscal deficit will continue to decline to 3.1% of GOP. Malaysia’s balance of payments position is expected to remain strong with the current account recording a surplus for the 11 th consecutive year. The current account surplus amounting to 13.0% of GOP will emanate from the goods and travels account. (Source: Economic Report 200712008) 6. INDUSTRY OVERVIEW (CONT’D)
6.1.2
Overview and Outlook of the World Economy The global economy is expected to continue expanding for the 5th consecutive year in 2007, albeit at a more moderate pace, amidst high crude oil prices and uncertainties in the economy of the USA. While growth is relatively lower than the 2006 performance, it is nonetheless expected to remain strong with further expansion in economic activities especially in fast­growing emerging economies, notably China, India and Russia as well as recovering Europe and Japan. Global inflation remains at manageable levels although it has edged upwards due to high crude oil prices. For advanced countries, growth is more balanced across regions with the steady recovery in Europe and Japan partially offsetting the moderation in the USA. Developing countries, primarily driven by investment and robust trade, are expected to outperform advanced countries and increasingly contribute to global growth. In this context, China, India and Russia are anticipated to account for more than half of this year’s growth. Rapid growth has also led several developing countries to significantly contribute to outward foreign direct investment (“FDI”), an area where traditionally, developed countries were the main sources. The more widely-spread growth in 2007 is expected to spill over into 2008, with world trade and investment projected to continue steadily expanding, and against a backdrop of relatively benign inflation. The favourable environment is expected to contribute positively to the Malaysian economy. In addition, Malaysia’s continued engagement in regional and multilateral cooperation is set to further deepen its integration with the global economy. Global growth in 2008, expected to be generally more-broad based both across regions and within countries, will continue to spur world trade and investment flows. Growth in world trade volume is projected at 7.4% in 2008 (2007:7.1 %) supported by steady demand-driven expansion in global-high technology industries, commodities and services. With regard to investment, global FDI is expected to remain strong, driven by rising merger and acquisition activities, sustained economic growth and an increase in fixed capital spending. Leading FDI recipients among the developed countries would be the USA, Belgium, Luxembourg, France and the United Kingdom while China, Hong Kong SAR, Singapore and India are expected to be the top four among the newly industrialised and emerging economies. (Source: Economic Report 200712008) 6. INDUSTRY OVERVIEW (CONT’D) 6.1.3
Overview of the Semiconductor Industry The semiconductor industry has been constantly evolving since the introduction of the first IC in the early 1970s. Early small-scale integration was mounted with only up to 100 electronic components per chip. Medium­scale integration increased the number of electronic components to 3,000, broadening the range of integrated logic available for computing and logic functions. Subsequently, the advent of large-scale integration had incorporated even larger logic functions (up to 100,000 electronic components), marking the manufacturing of the first microprocessor on a single chip. Eventually, very large-scale integration (“VLSI”) that harbours over 100,000 transistors on a chip was made available in the market in the 1980s. Microprocessors with cache memory and floating point arithmetic units signified the contribution of VLSI. Today, to reflect further growth of the complexity, the term ultra large-scale integration was coined for chips with more than 1 million electronic components built-in. Historically, most if not all, semiconductor companies are vertically integrated across the industry value chain in that they design, fabricate, package and test semiconductors primarily in their own facilities. Advances in technology, competitive pressures as well as the increasingly high labour and capital costs, however, have contributed to a reshaping of the industry which saw the emergence of the specialisation and outsourcing models, as well as the segmentation of the industry along geographical lines. High labour costs in their developed home countries have prompted many major semiconductor companies to shift the labour-intensive semiconductor assembly and packaging processes to cheaper, developing countries in the Asia Pacific (ex-Japan) region. Outsourcing became a key trend, which saw an increasing number of semiconductor companies outsourcing part or all stages of the semiconductor manufacturing process to independent third parties. Several factors are driving this trend, including the increasing complexity and capital investment required in semiconductor manufacturing as well as competitive and time-to-market pressures. Also, increasing competition has created a need for semiconductor companies to reduce costs and shorten time-to-market, which can be achieved by specialising/focusing their resources on core competencies such as design and marketing, while non-core areas, such as manufacturing, could be outsourced to third parties. Throughout the years, it is observed that there are advances in manufacturing processes and technologies. These included, among others, the shrinking of IC size of from 0.181J to 0.131J, migration from 8-inch to 12­inch wafers and the introduction of new advanced packaging technologies such as flip-chip. As a result, semiconductor manufacturing has become increasingly more complex to the extent that it has become a high technology industry. 6. INDUSTRY OVERVIEW (CONT’Dj 6.1.4
The capital investment involved has also ballooned significantly, pushed by the need to continuously upgrade and replace expensive manufacturing equipment with better and more efficient machines to keep up with technological advances and market demands. Since 1984, breakthroughs in EDA technology have improved the productivity of design engineers and rendered computer-automated design possible. Through EDA, chip design has become a more accessible and independent activity. After the introduction of EDA, the decoupling of design from manufacture led to the proliferation of independent fabless design houses. This allows design specialists to no longer worry about the huge amounts of capital. (Source: IMRR) Ie Design Industry The IC design industry is a kind of knowledge-intensive manufacturing­supporting service. It creates its innovative competencies and high added value through developing intellectual property. IC design ventures often provide points of entry for talented people who possess new product technologies and intend to start up their own businesses without financial support from the government or big capital. Since the establishment of a small design house needs relatively little capital and few engineers to initiate, most ambitious entrepreneur engineers or technopreneurs venture into this path to enter the semiconductor industry. Some small design houses specialise in certain types of design for customised chips, subcontracting fabrication to the IC manufacturing companies. After the fabrication stage, some design houses do their own testing, while others leave this to the other companies along the semiconductor value chain. The IC design industry is characterised by specialist companies that are good at a single product. Each IC design company bets on one major product and together they create a diversified and complete design product system. For example, most of the ASIC are used by consumer electronic companies who intend to exploit the advantages of the proprietary IC devices to differentiate their products from those of their competitors. The rise of ASSPs enriches the variety of IC devices produced in the semiconductor industry. It has allowed IC design houses to design all types of products, from chipsets to LAN sets, for individual customers and for open­market sales. These types of design-intensive and low to medium volume products provide some IC design companies with market niches, in which competitive advantage is based more on timing than on price. The explosive growth in silicon capacity and consumer usage of electronic products has pressured the design technology communities to quickly harness its potential. The more sophisticated the customer’s demands, the more advanced the IC designer’s capability must become. Once the customer and chip design house agree on the purpose of a chip, the design process commences. A typical design process includes architecture, logics, circuit, verification, layout, test, approval of design and release to fabrication. 6. INDUSTRY OVERVIEW (CONT’D) As the costs of low volume semiconductor production decline, application specific design has helped the relatively small design companies to start up and survive. They can be sustained by the large number of medium-sized computer peripheral and consumer product companies who employ both ASICs and ASSPs to help differentiate their products in the market. Thus, IC design houses that accumulate ASIC design capabilities will grasp the opportunities presented by ASICs and be able to take advantage of the trend toward product differentiation in the new competitive arenas. (Source: IMRR) 6.2 BARRIERS TO ENTRY 6.2.1 High R&D Resource Requirement Development of SoC requires a massive upfront investment in technology which will discourage potential entrants. Software is one of the major components contributing to the ascending cost. Moreover, there is no real independent software industry to serve this business. The design companies must either develop their own software tools or purchase them from the vendors. After the development of their own software, there is an additional cost element in the registration of IPs or filing of patent for the software. ASIC designs typically require a substantial investment in NRE costs. NRE cost refers to the one-time cost of engineering effort or product development in ASIC design, a fixed expense associated with a customer-specific adaptation of a standard application I product. Due to the fact that ASIC are “application-specific”, every new product involves specific designing requirement with the main bulk of cost being the engineering cost. The cost could range from USD500,OOO to USD10,OOO,OOO for one structured ASIC designs and higher for ASIC designs. Since this NRE is “fixed”, the product is economically feasible only if economies of scale could be achieved as high volume of production would dilute the “fixed” NRE cost. Apart from trying to achieve high volume, attempting to get the products to the market quickly is another challenge. Some companies have spent years developing a new product, and then found that it is already obsolete by the time it is released. To shorten the “time-to-market”, some companies are forced to pay high prices to purchase third party IP/patents from the vendors. This will increase the production cost ineVitably and reduce the profit for the companies. 6.2.2 Shortage of Skilled Personnel R&D in the IC design houses entails high expertise to operate and lead the team, which is not easy to be built, and costly to maintain. Some big companies commission hundreds of engineers for numerous years to develop the tools needed. Factors like intense competition and technological innovations continuously drive the demand for skilled personnel. In addition, due to rapid technology changes, skilled personnel have to be constantly trained to keep up with the latest developments. 6. INDUSTRY OVERVIEW (CONT’D) 6.2.3 6.2.4 The pool of chip designers available in the Malaysian job market is quite limited. Also, there are very few local universities that offer courses dedicated to aspiring chip designers. The problem with the shortage of skilled personnel is compounded by the fact that fresh university graduates are often given only very fundamental training. They would thus need a few years of hands­on and on-the-job experience to be able to function as capable chip design engineers. Although these engineers are given training by their employers, their retention is another issue. Sometimes, the local fabless companies may have to engage skilled personnel from abroad, incurring higher overheads. Patents and IPs The blocks of logic or data that are used in making an ASIC for a product is described as IP cores. The trend of implementing entire systems on an ASIC is creating a market for IP cores. There are designs created by leading third parties, offered access in catalogues, and sold to users for incorporation into large systems. By using these IP cores, a customer can essentially reduce its time-to-market and engineering effort. A company that has the capability to build its own IP cores forms one of the strongest barriers to entry to new entrants and raises the competitive bar against those who lack the capability. Completed designs with documented IPs not only can be re-used within the company but also marketed to third parties if needed. The advantages of a company having its own IP cores include lower development cost and shorter time-to-market. Although the current practice of documenting IP cores involves large up-front licensing and processing fees reminiscent of ASIC NRE charges, it has still become increasingly important to control design complexity and to protect the manufacturer’s I designer’s benefits. Need for Specialisation The semiconductor industry is a vast industry with numerous end user application markets such as consumer electronics, IT, automotive, medical devices, etc. Hence the design and technological skills have become more specialised to cater for a specific application market, with application-specific domain knowledge and experiences being compulsory. Designing ASIC for certain specific application markets requires more than generic knowledge. For application markets such as aerospace, medical, automotive, etc., specific knowledge and technological skills acquired by incumbent players form a barrier to entry for companies involved in other markets to venture into the markets dominated by the incumbents. In addition, to differentiate itself from other similar IC design houses, there must be competitive strengths in terms of speed, cost, flexibility and quality of providing design implementation services. (Source: IMRR) 6. INDUSTRY OVERVIEW (CONT’D) 6.3 GOVERNMENT LEGISLATIONS, POLICIES AND INCENTIVES
6.3.1
Legislations To encourage the development of a knowledge-based nation, the Government is committed to providing a comprehensive regulatory framework to protect IPs and encourage innovation, facilitating the development of an effective and efficient multimedia environment in Malaysia. IP protection comprises patents, trademarks, industrial designs, copyrights and layout designs of integrated circuits. Components of the Government’s regulatory framework include, inter alia: Patent Act 1983 In accordance with trade-related aspects of intellectual property rights (“TRIPS”), the Patent Act 1983 stipulates that the protection period of a patent is 20 years from the date of filing of an application. Under the Patent Act 1983, the utility innovation certificate provides for an initial duration of 10 years protection from the date of filing of the application. The owner of a patent has the rights in relation to the patent to exploit the patented invention, to assign or transmit the patent, and to conclude a license contract. Trade Marks Act 1976 The Trade Marks Act 1976 provides protection for registered trademarks and service marks in Malaysia. Once registered, only the registered proprietor or registered user of the trademark may use them and infringement action can be initiated against abusers who use marks without consent. The period of protection is 10 years, renewable for a period of every ten years thereafter. The proprietor of the trademark or service mark has the right to deal or assign as well as to license its use. Industrial Design Act 1996 The Industrial Designs Act 1996 provide that the rights of an owner in respect of a registered industrial design are personal property and are capable of assignment and transmission by operation of the law. Industrial designs must be new and do not include a method of construction or design that is dictated solely by function. Registered industrial designs are protected for an initial period of five years which may be extended for another two 5-year terms, providing a total protection period of 15 years. Lavout Design of Integrated Circuit Act 2000 The Layout Design of Integrated Circuit Act 2000 provides for the protection of layout designs of integrated circuits based on originality, creator’s own invention and the fact that the creation is freely created. The duration of protection is 10 years from the date of its first commercial exploitation or 15 years from the date of creation. The Layout Design of Integrated Circuit Act 2000 is implemented in compliance with the TRIPS agreement to provide a guarantee to investors in Malaysia’s electronics industry and to ensure the growth of technology in the country. 6. INDUSTRY OVERVIEW (CONT’D) 6.3.2
Copyright Act 1987 The Copyright Act 1987 is to make better provisions in the law relating to copyright. Literary works, musical works, artistic works films, sound recordings, broadcasts and derivative works is protected automatically if sufficient effort has been expended to make the work original in character and the work has been written down, recorded or otherwise reduced to a material form. The Copyright Act 1987 also specifies the circumstances amounting to and remedies for infringements and offences. The Copyright (Amendment) Act 1997 which amended the Copyright Act 1987, provides for unauthorised transmission of copyright works over the Internet as an infringement of copyright. It is also an infringement of copyright to circumvent any effective technological measures aimed at restricting access to copyright works. Policies Under the 9MP, the Government will continue to promote the development of the electronics industry, in view of its extensive linkages to the national economy. Besides attracting the multinational corporations (“MNCs”), the domestic manufacturers will be encouraged to focus on improving the sophistication level of their products, in terms of quality, functionality and design. This is to facilitate the development of the relevant skill sets and expertise, technology know-how and R&D capabilities to move the electronics industry further up the value chain. As many of these supporting industries to the electronics industry falls under the small-medium enterprise (“SME”) category, the government plans to formulate strategies that will propel the SMEs up the value chain into strong knowledge-intensive and value creating entities in the manufacturing sector, so as to meet the challenges of globalisation. There will be increased emphasis placed on technology development capabilities to establish technological leadership, achieve product and services differentiation as well as to create a larger number of local technology-based companies. This is through the provision of appropriate infrastructure, technology transfer and better access to financing. The R&D focus in the semiconductor industry is anticipated to cover fabrication, test and failure analysis, digital and analogue design of IC and advanced microelectronics. Under the Third Industrial Master Plan 2006-2020 (“IMP3”), the electronics industry is envisaged to continue to grow and contribute significantly to industrial progress and transformation. The MNCs will continue to assume a significant role in increasing the technology level of the industry, in tandem with the global trend in miniaturisation and convergence of technologies in multifunctional product. Testing activities will be part of the development of the entire semiconductor value chain. Towards realising the objectives and targets set for the electronics industry, 7 strategic thrusts have been established and they are as follows: • Strengthening the semiconductor industry through the establishment of a fully developed semiconductor cluster covering the north­western corridor in the peninsula, including Penang, Perak, Kulim High Technology Park and the neighbouring industrial areas of Kedah;
6. INDUSTRY OVERVIEW (CONT’D)
• Enhancement of the information and communications technology (“ICT”) industry value chain. The value chain, presently centred around the MSC in the Klang Valley, will be progressively expanded to designated areas around the country;
• Intensifying specialisation of R&D and design activities and the creation of R&D centres in the public universities and research institutes, so as to facilitate the development of new and emerging technologies;
• Promoting the application of new and emerging technologies like nanotechnology, micro electromechanical systems, photonics, wireless technologies and advanced display technologies to encourage the improvement of the competitiveness of domestic companies;
• Measures will be undertaken to nurture the existing domestic companies with the growth potential to expand and integrate into the regional and global supply chain networks, as well as become major producers on their own;
• Making available a sufficient supply of highly skilled and innovative workforce
• Strengthening the institutional support for the development of the electronics industry which includes the formulation of a standardised quality control management system, management and disposal of scheduled wastes and strengthening the role of industry associations.

6.3.3
Incentives Incentives for MSC status companies MSC status is the recognition by the Government through the MDeC to companies that participate and undertake ICT activities in the MSC. Companies with MSC status enjoy a set of incentive and benefits that is backed by the Government’s Bill of Guarantees. The incentives enjoyed by MSC status companies are: • Pioneer status with a tax exemption of 100% of the statutory income for a period of five years for the first round, or an Investment Tax Allowance (“ITA”) of 100%, and
• Eligibility of R&D grants (for majority Malaysian-owned MSC status companies).

6. INDUSTRY OVERVIEW (CONT’D) Other benefits include: • Duty free import of multimedia equipment;
• IP protection and a comprehensive framework of cyberlaws;
• No censorship of the Internet;
• Globally competitive telecommunication tariffs and services;
• High-powered implementation agency, the MDeC, to provide consultancy and assistance within the MSC;
• High quality, planned urban development;
• Excellent R&D facilities; and
• Green and protected environment.

Key ASIC obtained its MSC status from MDeC on 14 April 2006 and currently is enjoying full income tax exemption under the pioneer status for a period of 5 years and is renewable for another 5 years term. ” Incentives for a Knowledge-based Economy Malaysia is in the process of transforming itself from a production-based to a knowledge-based economy. To further encourage companies to invest in knowledge-intensive activities, certain companies that qualify will be granted “Strategic Knowledge-based Status”. These companies must have the following characteristics: • The potential to generate knowledge content;
• High value-added operations;
• Usage of high technology;
• A large number of knowledge-based workers; and
• Possess a corporation knowledge-based master plan.

Companies granted “Strategic K-based Status” are eligible for the following incentives: • Pioneer status with a tax exemption of 100% of the statutory income for a period of 5 years; or
• ITA of 60% on the qualifying capital expenditure incurred within 5 years. The allowance can be offset against 100% of the statutory income in the year of assessment.

‘” Incentives for R&D To further strength Malaysia’s foundation for more integrated R&D, companies which carry out design and prototyping as independent activities are also eligible for incentives. 6. INDUSTRY OVERVIEW (CONT’D) Main Incentives for R&D a. Contract R&D Company A contract R&D company, i.e., a company that provides R&D services in Malaysia to a company other than its related company, is eligible for: • Pioneer status with a tax exemption of 100% of the statutory income for 5 years; or
• ITA of 100% on the qualifying capital expenditure incurred within 10 years, which can be offset against 70% of the statutory income in the year of assessment.

b. R&D Company A R&D company, i.e. a company that provides R&D services in Malaysia to its related company or to any other company, is eligible for an ITA of 100% on the qualifying capital expenditure incurred within 10 years. The allowance can be offset against 70% of the statutory income in the year of assessment. Should the R&D company opt not to avail itself of the allowance, its related companies can enjoy a double deduction for payments made to the R&D company for services rendered. Eligibility: • Research undertaken should be in accordance with the needs of the country and bring benefit to the economy;
• At least 70% of the income of the company should be derived from R&D activities;
• For manufacturing-based R&D, at least 50% of the workforce of the company must be appropriately qualified personnel performing research and technical functions; and
• For agriculture-based R&D, at least 5% of the workforce of the company must be appropriately qualified personnel performing research and technical functions.

c. In-House Research A company that undertakes in-house R&D to further its business can apply for an ITA of 50% on the qualifying capital expenditure incurred within 10 years. The company can offset the allowance against 70% of its statutory income in the year of assessment. d. Second Round Incentives R&D companies/activities mentioned in categories (i) -(iii) will be eligible for a second round of Pioneer status for another five years, or ITA for a further 10 years, where applicable. 6. INDUSTRY OVERVIEW (eONT’D) e. Double Deduction for R&D • A company can enjoy a double deduction on its revenue (non-capital) expenditure for research which is directly undertaken and approved by the Minister of Finance;
• Double deduction can also be claimed for cash contributions or donations to approved research institutes, and payments for the use of the services of approved research institutes, approved research companies, R&D companies or contract R&D companies;
• Approved R&D expenditure incurred during the Pioneer Status period will be allowed to be accumulated and brought forward and be given another deduction after the Pioneer Status period; and
• Expenditure on R&D activities undertaken overseas, including the training of Malaysian staff, will be considered for double deduction on a case-by-case basis.

(Source: IMRR) The rest of this page is intentionally left blank 6. INDUSTRY OVERVIEW (CONT’D)
6.4 MAJOR PLAYERS AND COMPETITION There are a total of 15 local fabless IC design houses in Malaysia, mostly located and operating in the MSC area. This number excludes the MNCs located in Malaysia such as Intel that possess fabless houses that design ICs primarily to meet their own internal requirements. The total revenue generated by the major local fabless IC design houses amounted to approximately RM130 million in 2006. These fabless companies in Malaysia are relatively new and small (some with less than 10 employees). Although most of them employ both analogue and digital technology (thus theoretically enabling them to produce all analogue, mixed signals and digital products), their product range is more focused, with each of them trying to establish themselves in their respective niche application markets. Our Group ranked first among the local fabless IC design houses, with an estimated market share of 39.1 % in 2006. On the international front, the fabless market is a huge market with revenue registering approximately USD50 billion in 2006, up 27% from USD39 billion registered in 2005. Some of the major international fabless IC companies with business activities that are comparable to our Group are Faraday Technology Corporation, LSI Corporation, Mediatek Inc., Vimicro International Corporation and . Ali Corporation. Their business activities primarily focus on the research, design, development and marketing of complex high-performance ICs including, but not limited to, SoC, analogue, digital and mixed-signal ASIC/ASSP products. Their IPs and ICs target the consumer electronics, multimedia and communication application markets. Collectively, these companies registered around USD6.1 billion in revenue and USD1.2 billion in PAT as at their latest respective financial reporting dates. (Source: IMRR) 6.5 SUBSTITUTE PRODUCTS There is no direct substitute for the analogue, digital and mixed signal ASIC due to the versatility and the increasing complexity of the designs as the IC industry continues to grow. Unlike the market for digital ASICs which is characterised by a very large number of suppliers and by the readiness of customers to switch suppliers if they are offered a better combination price/performance ratio, analogue/mixed signal ASIC solution providers and their customers strive to build mutually beneficial partnerships. SoC devices are primarily dedicated devices designed to penetrate a mature, high­volume market, where the potential life expectancy of a product is relatively long and there is no need to continuously improve the SoC. This is due to its relatively longer time-to-market and higher development cost as compared to its closest substitute, the System-in-Package (“SiP”). However, the primary advantages of selecting SoC technology are due to its high performance, higher levels of device integration and high volume vis-ell-vis SiP. (Source: IMRR) 6. INDUSTRY OVERVIEW (CONT’D) 6.6 PROSPECTS AND OUTLOOK OF THE INDUSTRY 6.6.1 Key Industry Growth Drivers The fabless semiconductor industry has been the segment with the highest growth rate for the past few years in the semiconductor industry. For the 5­year period from 2002 to 2006, this particular segment of the industry achieved an impressive 36% compound annual growth rate in revenue. For 2006, the fabless revenue was reported to be approximately USD50 billion which translated to a 27% year-on-year growth. Worldwide SoC market is estimated to be worth more than USD43 billion by 2009. 6.6.2 Expanding Semiconductor Market The constant growth of the global economy has ensured the expansion of the semiconductor market. Global sales of semiconductors increased by 8.9% in 2006, mainly due to strong growth in consumer electronics and favourable economic conditions in the major world markets. China is a critical component of the global semiconductor industry, and is expected to increase its worldwide semiconductor market share to 26% in 2008 driven by the growth of wafer manufacturing plants and fabless companies. The country has become the manufacturing base for the global consumer electronics industry. The high energy prices that have dampened the economy growth in 2005 and 2006 did not affect consumer demand for electronics as bad as was originally anticipated. Conversely, the demand for the end products became much stronger than expected. Wireless handset sales hit 23% growth in 2006 with similar strong increases in the sales of digital televisions, digital cameras and MP3 players. After 2 quarters of sluggish sales, the electronics industry in Malaysia is experiencing an increase in orders for its products in the second half of 2007. Going forward, amid a sudden surge in demand, there could be a shortfall of foundry capacity worldwide by the end of 2007 and into 2008. 6.6.3 Strong Growth in the Asia Pacific Market The Asia Pacific has been an increasingly important market for the semiconductor industry with an increasing worldwide market share. This market possesses tremendous opportunities for companies operating in the semiconductor industry, especially with the increasing outsourcing activities in the region. The Asia Pacific region’s (ex-Japan) market share to total worldwide semiconductor sales has grown from 25% in 2000 to 46% in 2005. 6. INDUSTRY OVERVIEW (CONT’Dj Semiconductor Sales by Region 2000 Asia  Europe  Pacific  21o/d  25%
Japanr–t ~ 23%IV.”. United States 31% 2005 Europe 17% (JAsia PacificJapan~ 19%~ 46% United States
18% Source: D&B Malaysia Research 6.6.4 Increasing Capital Investments Compared to the general semiconductor industry’s market which is highly cyclical in nature, the fabless segment has been enjoying high growth for the past few years. This trend is expected to continue and gain further momentum. As a result, fabless companies are attracting investors to provide capital investments with the expectation of good returns. The availability of funds will be a catalyst to R&D activities and is beneficial to the market growth. 6.6.5 Technological Advances The other important growth factor of the semiconductor industry is technological advances. The semiconductor industry allocates significant amount of funds for R&D. The advances in basic knowledge then fuel the industrial progress. It is remarkable that, despite significant technological challenges, the industry is able to maintain the pace predicted by Moore’s Law -the doubling of transistors every 2 years. At the same time, transistor speed continued to improve at the record improvement rate of 17% per year. The rapid technological advancements enable the industry to widen the application markets, lower the price of the end products and introduce new products. The advent of innovative products has also created new markets. 6. INDUSTRY OVERVIEW (CONT’D)
6.6.6 New Emerging Market Segments New emerging market segments include the medical and aerospace industries. Due to the ageing global population, the demand for healthcare products in both developed and developing countries has steadily increased. Advances in technology are giving rise to new therapeutic modalities, which in turn are addressing more medical problems and aiding in prevention, early diagnosis and intervention of diseases. As a result, hefty investments have been injected into the semiconductor industry for the development of implantable medical devices, hearing aids, medical imaging systems, patient monitoring systems, and other applications. The overall aerospace and military industry is experiencing positive growth especially after the 911 tragedy. Predictably, this segment of the industry suffers from Ie component obsolescence and is requiring constant system reviews and updates. (Source: IMRR) The rest of this page is intentionally left blank

 

13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D) 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence EXECUTIVE SUMMARY INTRODUCTION Historically, most if not all, semiconductor comparues are vertically integrated across the industry value chain in that they design, fabricate, package and test semiconductors primarily in their own facilities. Advances in technology, competitive pressures as well as the increasingly high labour and capital costs, however, have contributed to a reshaping of the industry which saw the emergence of the specialisation and outsourcing models, as well as the segmentation of the industry along geographical lines. High labour costs in their developed home countries have prompted many major semiconductor companies to shift the labour-intensive semiconductor assembly and packaging processes to cheaper, developing countries in the Asia Pacific (ex Japan) region. Outsourcing became a key trend, which saw an increasing number of semiconductor companies outsourcing part or all stages of the semiconductor manufacturing process to independent third parties. Several factors are driving this trend, including the increasing complexity and capital investment required in semiconductor manufacturing as well as competitive and tirne-to-market pressures. Also, increasing competition has created a need for semiconductor companies to reduce costs and shorten time-to-market, which can be achieved by specialising / focusing their resources on core competencies such as marketing, while non-core areas, such as manufacturing, could be outsourced to third parties. The capital investment involved has also ballooned significantly, pushed by the need to continuously upgrade and replace expensive manufacturing equipment with better and more efficient machines to keep up with technological advances and market demands. Since 1984, breakthroughs in electronic design automation (“EDA”) technology have improved the productivity of design engineers and rendered computer-automated design possible. Through EDA, chip design has become a more accessible and independent activity. After the introduction of EDA, the decoupling of design from manufacturing led to the proliferation of independent fabless design houses. This permits design specialists to venture into the semiconductor industry without the need for a huge amount of capitaL Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence THE EMERGENCE OF EAST ASIAN COUNTRIES Until quite recendy, chip design has indeed remained heavily concentrated, both geographically and organizationally. Geographically, chip design was restricted to a few centres of excellence, mainly in the US, but also in Europe and Japan. However, fundamental changes have occurred over the last few years in the location of chip design that is signalling a growing mobility. Of particular importance has been a massive geographic dispersion of chip design to leading Asian electronics exporting countries. Taiwan has emerged as a primary new location, with South Korea following closely behind, and chip design is rapidly growing in China, as well as in Singapore and Malaysia. An equally important enabling factor for the entry of Asian chip design houses was the emergence of global EDA tool vendors like Synopsys, CAD Design Software and Mentor Graphics. The design of application-specific integrated circuits (“ASICs”) requires well-defined procedures to develop and use cell libraries that contain design modules. To do this cost-effectively, a new design methodology was developed where the design requirements were implemented in a software language that described digital circuits at register transfer language. To implement this new design, access to increasingly sophisticated EDA tools was criticaL As these tools were available on the market, albeit at a very high price, this provided entry opportunities for Asian design companies. Also, as the effective usage of these tools always requires substantial tweaking and adjustments, these Asian companies were able to accumulate a broad set of capabilities related to the implementation of these increasingly automated design methodologies. Leading Asian system companies, particularly those from Taiwan, China and South Korea are emerging as new sources of chip design, as part of their strategies to establish themselves as new sources of innovation and global standards. This is also driven by new technologies. They include innovations in process technology for electronic components (especially semiconductors and displays), where Korean and Taiwanese companies are among the industry leaders. Asian companies are now producing innovations in the design of complex system architectures in market segments like digital consumer systems, wireless telecommunication systems and business process software. In a handful of emerging centres of excellence in Asia, sophisticated innovation and research capabilities appear to have followed the earlier development of electronics manufacturing capabilities. This is likely to add further to the development of Asia’s chip design capabilities. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence
Taiwan Taiwan has truly emerged as a global leader in the semiconductor industry and serves as the home of the world’s top integrated circuit foundries. In Taiwan, an important catalyst was the establishment of Taiwan Semiconductor Manufacturing Company in 1987 as a provider of contract chip fabrication services for design companies. This enabled Taiwanese chip design start-ups to gain privileged access to a low-cost, high-speed supporting manufacturing system that encompasses both assembly and test, and wafer fabrication. Overseas Taiwanese returnees from the Silicon Valley also played an important part in technology transfers. Most of them came back with plenty of experiences and training at mid-career from such companies as IBM, Intel, AT&T and Hewlett Packard. Once they assembled the required funds, they were capable of recombining their ideas and capital to create their own fortunes.
China There is no doubt that the centre of gravity of foreign direct investment (“FDI”) in the electronics industry is moving toward China, transforming the geography of global production networks within the region. Taiwanese computer companies that supply leading U.S. computer original equipment manufacturers have played an important pioneering role in integrating China into global production networks. Since the early 1990s, they have continuously move production from Taiwan to China. Until 1999, investment in China’s semiconductor industry lagged woefully behind similar investments in Korea and Taiwan. The turning point came in 2000. During that year, the Chinese government apparently made a strategic decision to rely on FDls to accelerate the development of this industry. The Chinese government realises that FDls can generate a critical mass, establishing new global dynamic clusters for semiconductor manufacturing. “There was also the huge domestic market for semiconductors that spurred the Chinese government to act. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence South Korea The South Korean semiconductor industry has grown rapidly, due to a combination of the Korean government’s aggressive promotion policies and large-scale investments by private companies. As a result, South Korea’s semiconductor industry currently leads the global market in memory semiconductors. In 1994, a historical milestone happened in the South Korean semiconductor industry. Samsung developed the world’s first 256 megabit dynamic random access memory (“DRAM”), surpassing the Japanese chip makers for the first time. The 256 megabit DRAM was a high tech memory semiconductor product that accumulates 256 million transistors· and 256 capacitors in a fingernail-sized chip. The widespread usage of personal computers (“PCs”) and the introduction of Windows 95 led to a tremendous need for DRAM. However, the recession in the late nineties led the DRAM market to shrink. This abrupt change in the market resulted in the remapping of the DRAM industry, due mainly to cost competitiveness. South Korea arose as a formidable chip maker to Japan and the latter started to withdraw from the DRAM industry.
Japan After years of watching Asia’s chip industry shift toward Taiwan and China, Japanese companies are once again investing heavily in semiconductors. The companies are driven in part by sheer competitive necessity, like the aggressive expansion plans of Chinese and Taiwanese companies. The current technology trends play into traditional Japanese strengths. Games, consumer electronics and wireless communications have emerged as some of the hottest markets in the electronics industry, and the country has been a dominant player in these fields. Another bright spot for the Japanese is the increasing use of semiconductors in automobiles (telematics) and the growing clout of Japan’s automotive industry. The average number of microcontrollers in each vehicle has jumped from 10 to 50 over the past decade. Hence, Japanese semiconductor manufacturers are happy to see Japan’s automakers expanding their presence in the global market. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence BUSINESS MODEL EVOLUTION Until the late 1980s, manufacturers of semiconductors were vertically integrated, combining both design and manufacturing functions. This type of business model was referred to as an integrated device manufacturer (“IDM”) model. However, over the last decade, the semiconductor industry has been transformed from a few highly-vertical, fully-integrated companies to a very large number of specialised, modular companies including fablite and fabless companies. This transformation was attributed to two (2) primary factors, namely: • the emergence of new markets that required rapid change of technology; and
• the increasing economies of scale in manufacturing.

 

IDM Model An IDM is a semiconductor company which designs, manufactures and sells Ie products. The IDM’s business model integrates research and development (“R&D”), software design, production, sales and marketing and process equipment manufacturing under one roof, in contrast to a fabless company that outsource production to a third-party foundry. An IDM created values in several ways: • minimising transaction cost involved in transferring design to manufacturing;
• utilising economies of scale in R&D; and
• vertical integration from product development and manufacturing to marketing which covers multiple steps in the industry value chain.

 

Fablite Model The fablite model is an evolutionary step between the IDM model and becoming a fabless semiconductor company. At this stage, the company owns and maintains its own foundry plant and wafer-making capability but have a policy of outsourcing part of its manufacturing requirement to merchant pure-play foundries. The model offers certain manufacturing advantages such as shared risks and ensuring better asset utilisation. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence

 

Fabless Model Due to the smaller size of the targeted application markets and relatively high fixed cost of customised manufacturing today, there is an emergence of pure design houses. These design houses do not own or operate semiconductor wafer fabrication facilities; hence they are referred to as fabless companies. The fabless outsourced business model is currently widely adopted and highly successful. Many players are now committing themselves to either the fabless or fablite model, while only a small number of players remain as IDMs. The main advantage in adopting the fabless model is that the company can concentrate its R&D resources on the end market without conunitting capital investment to the escalating cost of maintaining a state-of-art fabrication facility. Instead of making large capital investments to develop a new wafer fabrication line, a fabless company develops strategic and completely synergistic relationships with highly-capitalised wafer manufacturers. Fabless companies specialise in engineering-intensive tasks during the development and design stage of an IC, bringing expertise to the initial architecture definition, specification, creation, partitioning and semiconductor process selection. A fabless company usually provides all of the development tasks, including: • circuit design and simulation;
• physical design and verification; and
• production test hardware and software development.

Fabless comparues also provide all of the design-specific manufacturing tasks, such as production test, product engineering, program management and quality assurance. Capital and labour intensive tasks, such as mask fabrication, wafer fabrication and packaging, are subcontracted to their strategic partners. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence Customer-Owned Tooling Model (“COT”) Under the COT model, both the logical and physical designs are owned by the designers, who are the customers, while fabrication and packaging / testing are done by the suppliers. The designers will complete the design using their own tools and submit the design in graphic design station II (“GDSII”) database format to any IC design house. GDSII is the standard for IC layout data exchange in the IC industry. The IC design house will then provides layout design rules and spice models for process variations and verifies the GDSII. The design will be sent to the selected foundry according to designers’ preferences. The COT model allows customers to have more control over schedules, design, cost, development process and the choice of foundries to select from. Ie DESIGN HOUSE The IC design industry creates its innovative competencies and high added value through developing intellectual properties (“IPs”). IC design ventures often provide points of entry for talented people who possess new product technologies and intend to start up their own businesses without financial support from the government or big capital. Since the establishment of a small design house needs relatively little capital and few engineers to initiate, most ambitious entrepreneur engineers or technopreneurs venture into this path to enter the semiconductor industry. Some small design houses specialise in certain types of design for customised chips, subcontracting fabrication to the IC manufacturing companies. After the fabrication stage, some design houses do their own testing, wIllie others leave this to the other companies along the semiconductor value chain. The IC design industry is characterised by specialist companies that are good at a single product. Each IC design company bets on one major product and together they create a diversified and complete design product system. For example, most ASICs are used by consumer electronic companies who intend to exploit the advantages of the proprietary IC devices to differentiate their products from those of their competitors. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence The rise of application-specific standard products enriches the variety of IC devices produced in the semiconductor industry. It has allowed IC design houses to design all types of products, from chipsets to local area network sets, for individual customers and for open-market sales. These types of design-intensive and low to medium volume products provide some IC design companies with market niches, in which competitive advantage is based more on timing than on pnce. The explosive growth in silicon capacity and consumer usage of electronic products has pressured the design technology communities to quickly harness its potential. The more sophisticated the customer’s demands, the more advanced the IC designer’s capability must become. Once the customer and chip design house agree on the purpose of a chip, the design process commences. A typical design process includes architecture, logics, circuit, verification, layout, test, approval of design and release to fabrication.
SUBSTITUTES There is no direct substitute for the analogue, digital and mixed signal ASICs due to the versatility and the increasing complexity of the designs as the industry continues to grow. Unlike the market for digital ASICs which is characterised by a very large number of suppliers and by the readiness of customers to switch suppliers if they are offered a better combination price / performance ratio, analogue / mixed signal ASIC solution providers and their customers strive to build mutually beneficial partnerships. System-on-Chip (“SoC”) devices are primarily dedicated devices designed to penetrate a mature, high-volume market, where the potential life expectancy of a product is relatively long and there is no need to continuously improve the Soc. This is due to its relatively longer time-to-market and higher development cost as compared to its closest substitute, the System-in-Package (“SiP”). However, the primary advantages of selecting SoC technology are due to its high performance, higher levels of device integration and high volume vis-a.-vis SiP. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence
INDUSTRY LINKAGES Basically, semiconductor products are microprocessors which form the basic circuitry elements for the functioning of other electronic and electrical products. The production of semiconductors comprises five (5) steps or processes, which are design, mask, fabrication, assembly and testing of chips. Since the establishment of the first semiconductor plant in 1972, the semiconductor industry has developed rapidly to become one of the countty’s major industries within the manufacturing sector. At that time, many foreign investors flocked into the country to take advantage of the abundant and cheap labour. Although the activities of chip manufacturing in the country are mainly dominated by lower-end assembly and testing of semiconductor devices, the industry is gradually moving into higher-end chip manufacturing technology, via backward integration into silicon ingot growing, cutting and polishing of silicon wafers, IC design and wafer fabrication. Malaysia is currently among the world’s leading sites for semiconductor assembly, testing and packaging. The electronics industry remained the leading contributor to export earrungs, investments, industrial output and employment in the country. The continued presence of multinationals (“MNCs”) has benefited the industry, in terms of technological progress and skills development. It has also encouraged the development of locally-owned supporting industries, in the supply of equipment, materials, component parts and dedicated services. There is a migration up the value chain to more complex and high-end products, as reflected by a higher percentage of capital investment per employee ratio throughout time. Other activities along the value chain of the electronics industry include R&D, marketing, distribution, logistics and procurement.
BARRIERS TO ENTRY The barriers to entry into the IC design industry are as follows: • High R&D Resource Requirements;
• Shortage of Skilled Personnel;
• Patents and IPs;
• Analogue / Digital / Mixed-Signal Design Capability; and
• Need for Specialisation.

Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence
CRITICAL SUCCESS FACTORS The critical success factors in the IC design industry are as follows: • Foundry Support;
• Possession of a Team of Experienced Designers;
• Ability to Integrate;
• Need for Relatively Lower Cost Structure;
• Need to Focus on Niche Markets;
• Strategic Partnerships between Foundries and Design Houses;
• Need to Gain Trusts among Customers.

 

CHALLENGES AND RISK FACTORS The challenges and risk factors in the IC design industry are as follows: • Cyclical Nature of the Semiconductor Industry;
• Impact of Macro Factors;
• Achieving Economies of Scale;
• I”ack of Control; and
• Rapid Technological Changes.

 

MARKET SHARE There are a total of 15 local fabless IC design houses, mostly located and operating in the Multimedia Super Corridor. This number excludes the MNCs that possess in-house facilities that design ICs primarily to meet their own internal requirements. The total revenue generated by the major local IC design houses amounted to approximately RM130 million in 2006. In revenue terms, Key ASIC is ranked fIrst among local IC design houses with an estimated 39.1% market share in the same year. On the international front, the fabless market is a huge market with revenues registering approximately USD50 billion in 2006, up 27% from USD39 billion registered in 2005. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence ApPLICATION MARKETS ICs have always been the key technology for developing consumer electronics and communication devices. In the world today, the increasing demand to integrate different functions and components into one unit with high performance and low cost has driven the enhancement of IC solutions.

 

MP3 Players A MP3 player is a battely-powered device that saves, organises and plays digital music according to its compatible me formats such as windows media audio and MP3. These flles can be downloaded into the device from the Internet or PC and will be stored in a storage component within the device.
Digital Televisions (“DTVs”) A DTV is a system used by the telecommunication companies to broadcast moving pictures using digital signals. One of the advantages that a DTV has over analogue system is higher and better audio quality and reception, not to mention its superior image. DTV also has the capabilities to broadcast more channels in the same space and is able to provide interactive services.
Digital Cameras A digital camera is a device that captures photographs elecu·onically. It is also capable of capturing moving images and storing video. Unlike conventional cameras that use photographic fllms, digital cameras use memory storage, also known as memory cards, to store photographs as flles in digital format.
Mobile Phones Mobile phone is one of the most commonly used devices today. A third generation mobile phone has a semiconductor content of 25% more (than the previous generations) to support digital cameras, colour displays and wideband data capacity.
Voice over Internet Protocol (VoIP”) VoIP is usually referred to as calls made over the Internet or Intranet. IP phones were introduced to make it easier for consumers to call directly from their computers as if they are calling using traditional networks. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence pes The PC market comprises both desktops and notebooks. As the market for desktops has already matured, a slow and gradual migration from desktops to notebooks had been observed. The massive expansion in Internet usage has spawned a whole new category of both hardware and peripherals to support communications applications. Wireless Fidelity (“Wi-Fi”) and Worldwide Interoperability for Microwave Access (“WiMAX”) Wireless connection uses wireless networks in computer systems for connectivity. Such connections enable consumers to surf the Internet without wires using laptops and mobile phones. Two (2) of the more popular wireless networks are Wi-Fi and WiMAX. CONCLUSION The Government is committed towards the further strengthening of the semiconductor industry through the establishment of a fully developed semiconductor cluster covering the north­western corridor in the peninsula, including Penang, Perak, Kulim High Technology Park and the neighbouring industrial areas of Kedah. The presence of indigenous design houses catering to the semiconductor industry represents a further step in the industry deepening of this vital industry, as the government is encouraging the expansion of the semiconductor value chain in the country through both forward and backward linkages, away from the traditional test and assembly activities. It also illustrates the extent of the local IC design industry’s involvement in the global production networks, as the semiconductors are mainly exported to be incorporated into other products. Despite the government’s persistent efforts to diversify the economy from the over reliance on the semiconductor industry, the latter is anticipated to play an important role in the country’s economy over the foreseeable future. Home-grown companies in the country have also played an increasing important role in the industrial deepening process, mainly through strategic partnerships with the MNCs. By utilising the local industry talent, valuable foreign exchange are saved instead of utilising the foreign based companies, through import substitution. The further development of the IC design industry will also assist to develop more knowledge workers, in line with the aspirations of the government to further expand human capital resources in the country. This is also in tandem with the transformation of the economy into a knowledge-based one. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007 13. EXECUTIVE SUMMARY OF INDEPENDENT MARKET RESEARCH REPORT (CONT’D)
Decide with Confidence The further development of IC design houses is crucial for the further industrial expansion of the semiconductor industry. The trend towards outsourcing in the semiconductor industry on the part of the foundries will also benefit IC design companies like Key ASIC. In today’s competitive business environment, many foundries are looking at outsourcing as a way to streamline time-to-market and minimise cost-to-manufacture, given the flexibility it provides. By outsourcing certain activities, the foundries can concentrate on their core activities of chip manufacturing and marketing. Although the semiconductor industry is highly cyclical with recurring periods of over supply, the wide range of application markets that the chips are used in means that different markets peak and bottom out at different times. Dun & Bradstreet (D&B) Malaysia Sdn Bhd © 2007

 

Comments are closed